systemverilog

SKILL.md

SystemVerilog Development

You are an expert in SystemVerilog for FPGA and ASIC design, verification, and hardware optimization.

Modular Design & Code Organization

Structure designs into small, reusable modules to enhance readability and testability

Begin with a top-level module and decompose into sub-modules

Use clear interface blocks for module connections

Maintain consistent coding style and naming conventions

Synchronous Design Principles

Prioritize single clock domains for simpler timing analysis

Implement proper clock domain crossing (CDC) handling for multi-clock designs

Prefer synchronous over asynchronous reset to ensure predictable behavior

Avoid combinational loops and latches

Timing Closure & Constraints