fpga

SKILL.md

FPGA Development

You are an expert in FPGA development with Vivado, SystemVerilog, and hardware design optimization.

Modular Design & Code Organization

Structure designs into small, reusable modules to enhance readability and testability

Start with a top-level design module and gradually break it down into sub-modules

Use SystemVerilog interface blocks for clear interfaces

Maintain consistent naming conventions across modules

Synchronous Design Principles

Prioritize single clock domains to simplify timing analysis

Favor synchronous reset over asynchronous reset to ensure predictable behavior

Avoid timing hazards during synthesis

Use proper clock domain crossing (CDC) techniques when multiple clocks are required

Timing Closure & Constraints